In the intensely competitive field of microelectronics, detailed analysis of a semiconductor integrated circuit product can provide valuable information as to how a particular technical problem was addressed, overall strengths and weaknesses of a design approach, and such matters. This information can be used to make decisions regarding market positioning, future designs, and new product development. The information produced from analysis of the product is typically provided through circuit extraction (reverse engineering), functional analysis, and other technical means. At the core of this activity is the process of design analysis which, in this context, refers to the techniques and methodology used to derive a complete or partial set of schematics from any type of integrated circuit manufactured using any process technology. For such technical information to be of strategic value it must be accurate and cost effective, and it is very important that the information should be generated in a timely manner.
A design analysis process typically involves skilled engineers manually extracting circuit information from a set of large “photomosaics” of an integrated circuit (IC). Skilled technicians and engineers perform the following sequential tasks:    (1) A high magnification image of a small portion of an IC is captured using a camera or electron microscope. The IC has been processed to expose a layer of interest.    (2) Step (1) is repeated for all of the various regions of interest of the layer of the IC, ensuring that sufficient overlap exists between adjacent images that will be used to create the photomosaics.    (3) Create Photomosaics: all adjacent photographs associated with the given IC layer are aligned and taped together.    (4) Steps (1)–(3) are repeated for every layer necessary to construct a layout database of the IC. All layers include interconnect layers. For example, four sets of photomosaics are required for a device with three layers of metal and one layer of polysilicon.    (5) Circuit Extraction: transistors, logic gates, and other elements employed in the IC are identified by manually, visually examining the polysilicon and lower metal interconnects photomosaics. Interconnections between circuit elements are traced and this information is captured in the form of schematic drawings. The drawings are manually checked against the photomosaics and any obvious errors are corrected.    (6) Organize Schematics: the schematic drawings are organized into hierarchical functional/logical blocks.    (7) Capture Schematics: the schematic drawings are entered into a computer using computer aided engineering (CAE) software tools for subsequent simulation and functional analysis of the IC.
The results of these substantially manual techniques for circuit extraction are often difficult to analyze. Difficulties arise in tracing signals that travel between several schematics. Locating the schematics associated with a particular signal can be very time consuming. During the circuit extraction process, signals are commonly given a generic name or label as a reference. Further analysis will reveal the purpose or function of these signals. The signals should then be renamed so that their name indicates their function. The signal renaming process creates two problems. Firstly, it takes some time to locate each schematic associated with a particular signal such that the signal can be relabeled on each schematic where it appears. Secondly, guaranteeing that the signal has been renamed on each schematic is difficult. This can result in inconsistencies with signal names that can confuse the engineer attempting to analyze the circuitry.
Another time consuming task associated with this manual circuit extraction process is the creation of signal and schematic lists. It is often useful to have a cross-reference between signal names and the name or number of the schematic in which these signals appear. However, such a cross-reference is very labor intensive to produce.
Once the schematics have been entered into a computer for simulation and/or subsequent analysis, it becomes difficult to edit the schematics. For example, as the circuit analysis progresses, it frequently becomes necessary to redraw certain schematics or to transfer portions of one schematic to another. Editing a set of schematics in such a way can often cause errors in the net list which require manual correction. Signal names and other labels on the revised schematics will also have to be manually changed.
Other than the manual method described above, the design analysis process can alternatively employ an automated circuit extraction process such as the one described in U.S. Pat. No. 5,694,481 which issued on Dec. 2, 1997 to Lam et al. Lam discloses an automated system for extracting design information from a semiconductor integrated circuit by imaging layers of an IC, creating a mosaic of the images, identifying the circuit elements, developing a basic net list of the circuit element connections, organizing the net list into functional blocks, and generating schematic diagrams.
Unfortunately, the circuit extraction method disclosed by Lam has the same restrictions as the manual method when in comes to locating signals and schematics, creating signal and schematic lists, and editing existing schematics. In fact, the automated method adds the burden of identifying logic gates and standard cells from a randomly organized net list. An engineer is required to sort through the schematics to convert the connected transistors into the relevant logic gates and standards cells. Obviously, this can take a very long period of time.
In order to organize numerous pages of schematics, analysts use schematic editing and simulating software such as Viewlogic/Innoveda's ViewDraw software. This software has a number of editing options that can be performed including operations such as cut, copy, paste, and search. However, these software packages were designed for integrated circuit designers rather then for analysts who reverse engineer integrated circuits and printed boards. The following limitations of ViewDraw create difficulties and inconveniences for users in organizing schematics:    1. The cut procedure does not preserve interconnections at the boundary of cells.    2. The paste procedure does not restore the wire or net interconnections that are lost for cells that are copied or cut elsewhere in the schematic.    3. There is no way to automate the connection of a selected net or wire to the appropriate nets or wires on a schematic page.    4. The signal and cell search is limited to a currently opened schematic page only and doesn't consider sublevels of a flat type project.    5. The search procedures do not provide very important information about objects such as: origin and destination of a signal, exact location in the project, and user descriptions (annotations) of objects.    6. There is no cell/gate search based on important properties such as: label, XY coordinates relative to the layout location of objects, and user defined attributes.    7. There are no global editing capabilities such as: adding or removing particular wires, labels, and/or cells for local signals and IN/OUT symbols.    8. There is no safe way of cutting a net or wire and preserving both ends and their labels. This is needed when manually disconnecting a gate, a block of gates or a cell from the rest of the schematic.
In the preparation of project reports regarding the results of a reverse engineered integrated circuit, hard copy printouts and Adobe Acrobat format documents are normally used. This limits customers in the ability to analyse the project data, to trace signals throughout the project schematic, and to follow the approach used in the design of the schematics. There is a need to create a project viewer that combines a schematic view, project objects and extended search capabilities.
Therefore, there is a need for an advanced schematic editor and navigator which would allow a user to manipulate the schematics of an entire project and to navigate through the entire project in order to analyse it.